Published on feb 2, 2023
The fifth generation of the Reduced Instruction Set Computer (RISC) architecture, known as RISC-V, was introduced in 2010. The RISC instruction set is an open standard for processors that is available for free under open source licenses. It is now possible to compile and run native images on RISC-V machines using GRAALVM.
GraalVM creates machine code using the Graal compiler by default. The most challenging aspect of supporting new architectures is developing the Graal compiler for those architectures. Additionally, the LLVM backend may be used, which allows users to support CPU architectures that are not currently supported by the GraalVM Native Image. LLVM contains several compiler and toolchain technologies that can be used as a backend for any instruction set architecture. The LLVM compiler is written in C++ and supports a variety of instruction sets, including x86-64, ARM, WebAssembly, and RISC-V.
As Linux runs relatively slowly on RISC-V machines, the binary may be cross-built on another architecture. For cross-building the application on another architecture, Sacha Coppey, who is working on GraalVM for Oracle Labs, provided instructions for setting up the environment with the RISC-V Toolchain, CAPCaches, and Static Libraries.
The performance differences between running a Micronaut application on a JVM and running a Native Image on RISC-V were evaluated using an example Micronaut application. Compared to a Native Image, the JVM startup time was approximately 9300 milliseconds.
GraalVM CE dev builds contain the Native Image LLVM backend for RISC-V based on Linux. LLVM supports most of the features of the other backends, but does not support macOS and other operating systems. Future optimizations may be possible by utilizing the RISC-V-specific features. A six-month implementation for RISC-V led the team to consider evaluating other environments, such as WebAssembly.
